List of HDL simulators
HDL simulators are software packages that simulate expressions written in one of the hardware description languages, such as VHDL, Verilog, SystemVerilog.
This page is intended to list current and historical HDL simulators, accelerators, emulators, etc.
Proprietary simulators
Some non-free proprietary simulators are available in student, or evaluation/demo editions. These editions generally have many features disabled, arbitrary limits on simulation design size, but are offered free of charge.Free and open-source simulators
| Simulator name | License | Author/company | Supported languages | Description |
| GPL2+ | VHDL-1987, VHDL-1993 | A project to develop a free, open source, VHDL simulator | ||
| GHDL | GPL2+ | Tristan Gingold | VHDL-1987, VHDL-1993, VHDL-2002, partial VHDL-2008 | GHDL is a complete VHDL simulator, using the GCC technology. |
| Icarus Verilog | GPL2+ | Maciej Sumiński Stephen Williams | VHDL preprocessor added that converts VHDL to Verilog | |
| nvc | GPL3 | Nick Gasson | VHDL-1993 |
Key
History
HDL simulation software has come a long way since its early origin as a single proprietary product offered by one company. Today, simulators are available from many vendors at various prices, including free ones. For desktop/personal use, Aldec, Mentor, LogicSim, SynaptiCAD,TarangEDA and others offer tool-suites under US$5000 for the Windows 2000/XP platform. The suites bundle the simulator engine with a complete development environment: text editor, waveform viewer, and RTL-level browser. Additionally, limited-functionality editions of the Aldec and ModelSim simulator are downloadable free of charge, from their respective OEM partners For those desiring open-source software, there is Icarus Verilog, GHDL among others.Beyond the desktop level, enterprise-level simulators offer faster simulation runtime, more robust support for mixed-language simulation, and most importantly, are validated for timing-accurate gate-level simulation. The last point is critical for the ASIC tapeout process, when a design database is released to manufacturing. The three major signoff-grade simulators include Cadence Incisive Enterprise Simulator, Mentor ModelSim/SE, and Synopsys VCS. Pricing is not openly published, but all three vendors charge $25,000-$100,000 USD per seat, 1-year time-based license.
FPGA vendors do not require expensive enterprise simulators for their design flow. In fact, most vendors include an OEM version of a third-party HDL simulator in their design suite. The bundled simulator is taken from an entry-level or low-capacity edition, and bundled with the FPGA vendor's device libraries. For designs targeting high-capacity FPGA, a standalone simulator is recommended, as the OEM-version may lack the capacity or speed to effectively handle large designs.